1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a semiconductor memory device including a potential generation circuit generating an internal power supply potential based on an external power supply potential.
2. Description of the Background Art
In dynamic random access memories (referred to as xe2x80x9cDRAMxe2x80x9d hereinafter), reduction in the internal power supply voltage is conventionally aimed as well as realizing microminiaturization and high integration of the structural elements.
FIG. 19 is a circuit block diagram showing the main part of such a DRAM. In the DRAM of FIG. 19, a voltage-down converter (referred to as VDC hereinafter) 70 down-converts an external power supply potential EXVCC to generate and provide to a sense amplifier 73 an internal power supply potential VCCS. VDC 71 down-converts external power supply potential EXVCC to generate and provide to a row decoder 72, a column decoder 75 and a data input/output buffer 76 an internal power supply potential VCCP. Each memory cell MC includes an N channel MOS transistor Q for access and a capacitor C for information recording. Row decoder 72 selects a word line WL out of a plurality of word lines WL. That word line WL is set to an H level (logical high) of the selected level. Accordingly, N channel MOS transistor Q of memory cell MC connected to that word line WL conducts, whereby a small potential difference is generated between a pair of bit lines BL and /BL that is already equalized to a bit line potential VBL.
The small potential difference generated between the pair of bit lines BL and /BL is amplified by sense amplifier 73 to internal power supply voltage VCCS. When a column select line CSL is driven to an H level (internal power supply potential VCCP) of the selected level by column decoder 75, a pair of N channel MOS transistors in column select gate 74 conducts, whereby the voltage between bit lines BL and /BL is transmitted to a pair of data input/output lines IO and /IO. Data input/output buffer 76 outputs externally a signal of a logic level corresponding to the voltage between the pair of data input/output lines IO and /IO (+VCCS or xe2x88x92VCCS) as readout data.
FIG. 20 is a block diagram showing a structure of a DRAM mounted on one chip together with an ASIC circuit (referred to as eDRAM hereinafter). Referring to FIG. 20, VDC 81a-81d are under control of a VDC activation signal VDCON to down-convert external power supply potential EXVCC to generate an internal power supply potential VCCS. Internal power supply potential VCCS is applied to each sense amplifier band SA and column decoder 84 in a memory mat 82. The peripheral circuits such as row decoder 83, data input/output buffer 85 and control circuit 86 are driven by internal power supply potential VCC for the ASIC circuit. The reason why column decoder 84 is driven by internal power supply potential VCCS for sense amplifier band SA is that, if column decoder 84 is driven by internal power supply potential VCC, data cannot be transferred between bit line pair BL and /BL and data input/output line pair IO and /IO shown in FIG. 19 since internal power supply potential VCC of the ASIC circuit is reduced to 1.2 V whereas internal power supply potential VCCS of sense amplifier band SA is approximately 2 V.
FIG. 21 is a circuit diagram showing a structure of VDC 81a. Referring to FIG. 21, VDC 81a includes P channel MOS transistors 90-93 and N channel MOS transistors 94-96. MOS transistors 90, 91 and 94-96 form a differential amplifier 97 that compares a reference potential VREF with an internal power supply potential VCCS.
Signal VDCON attains an H level of an activation level and an L level of an inactivation level in response to the input of an active command ACT and a precharge command PRE, respectively. When signal VDCON is at an L level of an inactivation level, P channel MOS transistor 92 is rendered conductive whereas N channel MOS transistor 96 is rendered nonconductive. Driver transistor 93 is fixed at the nonconductive state, and differential amplifier 97 is rendered inactive.
When signal VDCON attains an H level of an activation level, P channel MOS transistor 92 is rendered nonconductive whereas N channel MOS transistor 96 is rendered conductive, whereby differential amplifier 97 is activated. When internal power supply potential VCCS is lower than reference potential VREF, P channel MOS transistor 93 conducts to supply current to an output node N93. When internal power supply potential VCCS is higher than reference potential VREF, P channel MOS transistor 93 is rendered nonconductive, whereby the supply of current to output node N93 is ceased. Therefore, internal power supply potential VCCS is maintained at the level of reference potential VREF. Other VDC 81b-81d have a structure identical to that of VDC 81a. 
In the above-described eDRAM, column select line CSL is selected immediately after activation of the sense amplifier in the read and write operations. Furthermore, current consumption of column decoder 84 is great since the number of IOs is greater than that of a general purpose DRAM. Therefore, internal power supply potential VCCS will become lower than reference potential VREF unless the current supply capability of VDC 81a-81d is set large enough.
In order to increase the current supply capability of VDC 81a-81d, the size of driver transistor 93 is to be increased. However, simply increasing the size will degrade the response since the gate capacitance of transistor 93 becomes larger. In order to improve the response, the through current I flowing to N channel MOS transistor 96 must be increased.
FIG. 22 is a timing chart of through current I in VDC 81a-81d. There is the possibility of a read command READ or a write command WRT input to effect a column select operation during the amplify operation of sense amplifier 73 in response to the input of an active command ACT. Therefore, through current I is set to a constant I=Is+Id during the period of input of active command ACT up to input of precharge command PRE, where Is is the through current required during the amplify operation of sense amplifier 73 and Id is the through current required during a column select operation.
However, through current I is set to I=Is+Id even in an active standby state where neither an amplify operation of sense amplifier 73 nor a column select operation is carried out. Current consumption was wasted greatly in conventional cases.
In view of the foregoing, a main object of the present invention is to provide a semiconductor memory device of small current consumption.
According to an aspect of the present invention, a semiconductor memory device includes a first potential generation circuit generating a first internal power supply potential for a sense amplifier according to an external power supply potential, and a second potential generation circuit generating a second internal power supply potential for a column select circuit according to the external power supply potential. At least one of the first and second potential generation circuits has a controllable response with respect to change in the output potential during the activation period. By increasing the response of the first and/or second potential generation circuit during the period where current consumption of the first and/or second internal power supply potential is great, and lowering the response of the first and/or second potential generation circuit during other periods, the current consumption of the first and/or second potential generation circuit can be reduced. Thus, the current consumption of the semiconductor memory device can be reduced.
Preferably, the first potential generation circuit includes a first transistor connected between a line of the external power supply potential and a line of a first internal power supply potential, and a first differential amplifier comparing a first reference potential with the first internal power supply potential to control the conductive status of the first transistor according to the comparison result. The second potential generation circuit includes a second transistor connected between the line of the external power supply potential and a line of a second internal power supply potential, and a second differential amplifier comparing the first reference potential with the second internal power supply potential to control the conductive status of the second transistor according to the comparison result. The response of the first and second potential generation circuits is increased according to the driving current of respective first and second differential amplifiers. At least one of the first and second differential amplifiers has a controllable driving current. In this case, the first and second potential generation circuits can be implemented easily.
Preferably, there is provided a third potential generation circuit to generate the first reference potential, and first and second buffer circuits to transmit the first reference potential generated at the third potential generation circuit to the first and second differential amplifiers, respectively. In this case, transmission of the noise generated at one of the first and second differential amplifiers to the other can be prevented.
Further preferably, there are provided a third potential generation circuit to generate the first reference potential, and first and second filter circuits connected between the output node of the third potential generation circuit and respective input nodes of the first and second differential amplifiers to transmit the first reference potential and to remove noise. In this case, transmission of the noise generated at one of the first and second differential amplifiers to the other of the first and second differential amplifiers can be prevented.
Preferably, a plurality of sense amplifiers, a row select circuit, a first potential generation circuit and a second potential generation circuit are rendered active in response to the input of an active command. The column select circuit is rendered active for only a predetermined time in response to the input of either a read command or write command after input of the active command. In this case, the activation/inactivation of the plurality of sense amplifiers, the row select circuit, the first potential generation circuit, the second potential generation circuit, and the column select circuit can be controlled easily.
Preferably, the response of the first potential generation circuit is controllable. The response is set to a relatively high level during the period of time required for the amplify operation of a plurality of sense amplifiers after an active command is input, and set to a relatively low level at the elapse of that period of time. In this case, current consumption of the first potential generation circuit is increased only during the time required for the amplify operation of the plurality of sense amplifiers. The current consumption of the first potential generation circuit is lower at the remaining period of time. In average over the entire period of time, current consumption of the first potential generation circuit becomes lower than that of the conventional case.
Also preferably, the response of the second potential generation circuit is controllable. The response is set to a relatively high level during a predetermined time where the column select circuit is rendered active, and set to a relatively low level during the period other than that predetermined time. In this case, the current consumption of the second potential generation circuit is increased only during the period of time where the column select circuit is rendered active. Current consumption of the second potential generation circuit is reduced in the remaining period of time. In average over the entire period of time, current consumption of the second potential generation circuit is reduced than that of the conventional case.
Preferably, a plurality of second potential generation circuits are provided. During the predetermined time where the column select circuit is activated, all of the plurality of second potential generation circuits are rendered active. During the period of time other than that predetermined time, a second potential generation circuit among the plurality of second potential generation circuits is rendered active during the period of time other than the predetermined time. In this case, the response of the plurality of second potential generation circuits as a whole can easily be controlled.
Preferably, there are further provided a first capacitor arranged in the neighborhood of the plurality of sense amplifiers, and connected between the line of the first internal power supply potential and the line of the second reference potential to stabilize the first internal power supply potential, and a second capacitor arranged in the neighborhood of the column select circuit, and connected between the line of the second internal power supply potential and the line of the second reference potential to stabilize the second internal power supply potential. In this case, the first and second internal power supply potentials can be stabilized. Since the first capacitor and the second capacitor are arranged in the vicinity of the plurality of sense amplifiers and the column select circuit, respectively, the voltage drop can be suppressed effectively with a smaller capacitance than the conventional case where the internal power supply potential for the sense amplifier and for the column select circuit is generated by one potential generation circuit. Accordingly, the layout area can be reduced.
Preferably, a plurality of groups of a memory array, a plurality of column select gates, a plurality of sense amplifiers and a column select circuit are provided. The plurality of groups are arranged in a matrix to form a memory mat. The first capacitor is arranged in a distributed manner at a plurality of unoccupied regions of the memory mat and around the memory mat. In this case, the unoccupied region at the surface of the chip can be used effectively to allow reduction of the layout area.
Preferably, the second potential generation circuit is provided in the proximity of the column select circuit. Here, the current supply capability of the second potential generation circuit can be reduced since the voltage drop caused by the wiring between the second potential generation circuit and the column select circuit can be reduced. Also, the capacitance of the capacitor to stabilize the second internal power supply potential can be reduced. Thus, the layout area can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.